Solid state image pickup device

ABSTRACT

P type semiconductor well regions  8  and  9  for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region  8  at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer  1 A, for limiting a dark current generated at the end portion of the LOCOS layer  1 A. In addition, the second P type semiconductor well region  9  at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.

[0001] This application claims priority to Japanese Patent Application Number JP2002-059989 filed Mar. 6, 2002, which is incorporated herein by reference.

[0002] The present invention relates to a solid state image pickup device comprising a photo-electric conversion device for generating a signal charge according to the amount of light received, and a pixel transistor for reading out the signal charge generated by the photo-electric conversion device, in each of a plurality of pixels arranged in a semiconductor chip.

RELATED ART

[0003] In recent years, video cameras and electronic cameras have become very popular, and CCD type and MOS type solid state image pickup devices have been primarily used in these cameras.

[0004] Among these devices, the MOS type solid state image pickup device has a structure in which a plurality of pixels comprising photo-electric conversion devices (photodiodes; PD) respectively are arranged in a two-dimensional array to form an image pickup region. A floating diffusion (FD) portion and various other MOS transistors for transfer, amplification and the like are also provided in each pixel. The light incident on each unit pixel is subjected to photo-electric conversion by the photodiode to generate a signal charge. The signal charge is transferred to the FD portion by the transfer transistor and a potential variation in the FD portion is detected by the amplification transistor. The detected potential variation is converted into an electrical signal and is amplified, whereby a signal from each pixel is outputted through a signal conductor.

[0005] In such MOS type solid state image pickup devices, there is known one in which a plurality of layers of N type well regions are formed by injection of ions at different energy or by the injection of different species of ions, on the lower side of an N type well region constituting a charge accumulation region of the photo-electric conversion device, whereby a depletion layer is elongated in the depth direction so as to provide enhanced sensitivity.

[0006] In this case, a P type well region that forms a barrier for device separation and for preventing mixing of signal charges (mixing of colors) between the adjacent pixels must also be formed in a deep region in conformity with the N type well region of the photo-electric conversion device.

[0007]FIG. 2 is a sectional view showing the pixel structure of such an MOS type solid state image pickup device for achieving increased sensitivity.

[0008] The MOS type solid state image pickup device has a structure in which a P type semiconductor well region 110 is provided on an N type semiconductor region 111, and a photodiode PD and a pixel transistor Tr are provided in an N type semiconductor region 112. These layers are formed on the upper side of the P type semiconductor well region 110.

[0009] The photodiode PD includes a P type semiconductor region 106 provided as a positive hole accumulation layer at an uppermost layer of the N type semiconductor region 112. An N type electric charge accumulation region 105 is formed as a layer on the lower side of the P type semiconductor region 106. Additionally, an N type semiconductor region 107 is provided as a layer on the lower side of the N type electric charge accumulation region 105, whereby a depletion layer is elongated in the depth direction so as to provide enhanced sensitivity.

[0010] In addition, a P type semiconductor region 103 to be a channel of a transfer transistor Tr is formed adjacent to the photodiode PD, and an N type drain region 102 of the transfer transistor Tr is provided adjacent to the P type semiconductor region 103. This N type drain region 102 is the above-mentioned FD portion.

[0011] A gate electrode 104 consisting of a polysilicon film is provided on the upper side of the P type semiconductor region 103 with an insulating film (gate oxide film) 101 consisting of a silicon oxide film located therebetween. When a predetermined voltage is applied to the gate electrode 104, a signal charge accumulated in the photodiode PD is transferred into the N type drain region 102.

[0012] Incidentally, although other transistors are also provided in the pixel, the remaining transistors have no direct relation with the characteristic features of the present invention, so that description of these transistors has been omitted. The omitted operational characteristics are well known to those of ordinary skill in the art.

[0013] Additionally, for conventionally forming adjacent pixels, an insulating layer 101A for device separation constituted of LOCOS is provided in an upper portion of a silicon substrate at a boundary portion of the pixel. A P type semiconductor well region 113 as a channel stop region is provided as a layer on the lower side of the insulating layer 101A.

[0014] The P type semiconductor well region 113 is formed such that it is nearer to the pixel side than an end portion of the LOCOS layer 101A, for reducing a dark current generated at the end portion of the LOCOS layer 101A. This structure is formed to such a deep position as to reach the P type semiconductor well region 110 at the lower layer, consistent with the position of the high sensitivity type photodiode PD as above-mentioned.

[0015] However, in the case where the P type well region for device separation is formed deeply as above-mentioned, the amount of diffusion of ion species in the horizontal direction increases as the ion injection for the formation is conducted at higher energy.

[0016] Therefore, as shown in FIG. 2, the P type well region at a deep layer portion spreads to the side of the high sensitivity type photodiode PD. This thereby narrows the depletion region, whereby the sensitivity-enhancing effect is reduced, or shading characteristics are worsened.

[0017] In view of the foregoing, it is one object of the present invention to provide a solid state image pickup device in which it is possible to prevent a depletion layer of a high sensitivity type photo-electric conversion device from being obstructed by a well region that is used for device separation. The well region for device separation is formed deeply in the semiconductor substrate in conformity with the high sensitivity type photo-electric conversion device, and it is also possible to realize an effective enhancement of sensitivity and an improvement of shading.

[0018] Other objects and advantages of the present invention will be apparent in light of the following summary and detailed description.

SUMMARY OF THE INVENTION

[0019] In order to attain the above objects and advantages, an exemplary embodiment of the invention is characterized in that, a solid state image pickup device is comprised of a photo-electric conversion device for generating a signal charge according to the amount of light received, and at least one pixel transistor for reading out the signal charge generated by the photo-electric conversion device. A plurality of pixels are preferably arranged in a semiconductor substrate. In the preferred exemplary embodiment, well regions for device separation are provided at boundary portions between adjacent ones of the plurality of pixels. The well regions for device separation are each comprised of a plurality of layers of well regions in the depth direction of the semiconductor substrate, and the plurality of layers of well regions are so formed that the lower-layer well region is formed in a narrow region receding farther from each pixel than the upper-layer well region.

[0020] In the solid state image pickup device according to the present invention, the well regions for device separation are each comprised of a plurality of layers of well regions in the depth direction of the semiconductor substrate, and the lower-layer well region of the plurality of layers is formed in a narrow region receding farther from each pixel than the upper-layer well region. Therefore, in a constitution in which the well regions for device separation are formed deeply in the semiconductor substrate in conformity with the high sensitivity type photo-electric conversion device, it is possible to prevent a depletion layer of the high sensitivity type photo-electric conversion device from being obstructed by the well regions for device separation, and it is possible to achieve an effective enhancement of sensitivity and a shading-restraining effect.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a sectional view showing the pixel constitution of a MOS type solid state image pickup device according to an exemplary embodiment of the present invention; and

[0022]FIG. 2 is a sectional view showing the pixel constitution of a MOS type solid state image pickup device according to a related art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0023]FIG. 1 is a cross-sectional view that illustrates the pixel constitution of a MOS type solid state image pickup device according to the preferred exemplary embodiment.

[0024] The solid state image pickup device preferably has a structure in which a P type semiconductor well region 10 is provided on an N type semiconductor region 11, and a photodiode PD and a pixel transistor Tr are provided in an N type semiconductor region 12 at the upper side of the P type semiconductor well region 10 as shown.

[0025] The photodiode PD includes a P type semiconductor region 6 as a positive hole accumulation layer at an uppermost level above the N type semiconductor region 12, and an N type electric charge accumulation region 5 as a layer on the lower side of the P type semiconductor region 6. An N type semiconductor region 7 is provided as a layer on the lower side of the N type electric charge accumulation region 5, whereby a depletion layer is elongated in the depth direction so as to provide enhanced sensitivity.

[0026] In addition, a P type semiconductor region 3 forming a channel of a transfer transistor Tr is provided adjacent to such the photodiode PD, and an N type drain region 2 of the transfer transistor Tr is provided adjacent to the P type semiconductor region 3. The N type drain region 2 is the above-mentioned FD portion.

[0027] A gate electrode 4 consisting of a polysilicon film is provided on the upper side of the P type semiconductor region 3 with an insulating film (gate oxide film) 1 consisting of a silicon oxide film formed therebetween. When a predetermined voltage is applied to the gate electrode 4, a signal charge accumulated in the photodiode PD is transferred into the N type drain region 2.

[0028] It will be recognized that other transistors are also provided in the pixel, but these transistors have no direct relation with the characteristic features of the present invention, so that description of these transistors has been omitted. In addition, various wiring layers, upper-layer insulating films, and, further, an on-chip color filter, an on-chip micro-lens and the like are appropriately disposed in layers on the upper side of the gate electrode 4. However, these components have no direct relation with the characteristic features of the present invention, so that description of these components is omitted.

[0029] An insulating layer 1A for device separation constituted of LOCOS is provided at an upper portion of the silicon substrate, at a boundary portion of the pixel. Upper and lower layers of P type semiconductor well regions 8 and 9 are provided as channel stop regions as layers on the lower side of the insulating layer 1A.

[0030] The P type semiconductor well regions 8 and 9 are the well regions for device separation which constitute a characteristic feature of the present invention. In accordance with the preferred exemplary embodiment, the first P type semiconductor well region 8 is provided beneath the LOCOS layer 1A, and the second P type semiconductor well region 9 is provided as a layer on the lower side of the first P type semiconductor well region 8.

[0031] A lower end portion of the second P type semiconductor well region 9 preferably extends to the P type semiconductor well region 10, and constitutes a barrier in the structure of surrounding the depletion layer of the photodiode PD from lateral sides and the lower level.

[0032] The well regions 8 and 9 are formed as upper and lower layers by the injection of ions at different injection energy or the injection of different species of ions so that the P type semiconductor well region is formed down to such a deep position as to reach the P type semiconductor well region 10 at the lower layer, as described above.

[0033] The first P type semiconductor well region 8 at the upper layer is provided such that it is nearer to the pixel than an end portion of the LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A.

[0034] In addition, because the second P type semiconductor well region 9 at the lower layer is formed by injection of ions at high energy, the amount of diffusion of the impurity in lateral directions is large there.

[0035] In view of this characteristic, in order not to narrow the depletion layer which determines the range of collection of signal charges in the photodiode PD, the pattern of the second P type semiconductor well region 9 is formed in a narrow region receding farther away from the photodiode PD than the pattern of the first P type semiconductor well region 8 (namely, in the condition of being away from the N type electric charge accumulation region 5).

[0036] As a result, the depletion layer of the photodiode PD is prevented from being obstructed by the second P type semiconductor well region 9 formed at a deep position, and the depletion layer is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be realized.

[0037] In addition, by adopting such a structure, the depletion layer is broadened in the horizontal directions, so that quantum efficiency for skew light can be enhanced, and shading characteristics can be improved.

[0038] While the preferred exemplary embodiment of the present invention has been described above, the present invention is not limited to the preferred exemplary embodiment, and various modifications can be made.

[0039] For example, while in the preferred exemplary embodiment the upper and lower two layers of P type semiconductor well regions 8 and 9 are provided as described above, in an alternate embodiment, a design in which three or more layers of P type semiconductor well regions are provided may be adopted.

[0040] In addition, as the constitution of transistors in the pixel, it may generally be considered to provide, for example, a transfer transistor for transferring the signal charge generated in the photodiode PD to an FD portion, an amplification transistor for converting the potential variation in the FD portion into an electrical signal, a reset transistor for resetting the potential of the FD portion, a selection transistor for selecting an output of the amplification transistor, and the like. A variety of alternate designs, ranging from one in which the pixel is comprised of one transistor to a construction in which the pixel is comprised of not less than five transistors, have been proposed, and some of them have been put to practical use. The present invention is to be construed as being applicable to any of these systems. The list of alternate structures described above is not exhaustive and those skilled in the art will appreciate that other modifications may also be made which nonetheless fall within the scale of the claims.

[0041] As has been described above, a solid state image pickup device according to the present invention, the well regions for device separation are each comprised of a plurality of layers of well regions in the depth direction of the semiconductor substrate, and the lower-layer well region of the plurality of layers is formed in a narrow region receding farther from each pixel than the upper-layer well region. Therefore, in a constitution in which the well region for device separation is formed deeply in the semiconductor substrate in conformity with a high sensitivity type photo-electric conversion device, the depletion layer of the high sensitivity type photo-electric conversion device can be prevented from being obstructed by the well region for device separation. Consequently, an effective enhancement of sensitivity can be realized, and shading characteristics can be improved. 

What is claimed is:
 1. A solid state image pickup device comprising: a photo-electric conversion element for generating a signal charge according to an amount of received light; at least one pixel transistor for reading out said signal charge generated by said photo-electric conversion element; well regions for device separation provided between pixels, said well regions for device separation each comprised of plural layers of well regions in the depth direction of said semiconductor substrate; and wherein said plural layers of well regions are formed such that a lower-layer well region is spaced farther from an adjacent pixel than the upper-layer well region.
 2. A solid state image pickup device as set forth in claim 1, wherein a device separation insulating layer for separating adjacent pixels is provided at an upper layer portion of said device, and said well region for device separation is provided at a level below said device separation insulating layer.
 3. A solid state image pickup device as set forth in claim 2, wherein the upper-layer well region of said plural layers of well regions is located nearer to the photo-electric conversion element than an end portion of said device separation insulating layer.
 4. A solid state image pickup device as set forth in claim 1, wherein said plural layers of well regions constituting said well region for device separation are formed by injection of an ion at different injection energy or by injection of a different species of ions.
 5. A solid state image pickup device as set forth in claim 1, wherein said photo-electric conversion device is comprised of a P type semiconductor region located at an upper layer of said semiconductor, and an N type semiconductor region is located at a level under said P type semiconductor region.
 6. A solid state image pickup device as set forth in claim 1, wherein said N type semiconductor region of said photo-electric conversion device is comprised of a plurality of layers of N type semiconductor regions formed in the depth direction of said semiconductor.
 7. A solid state image pickup device as set forth in claim 1, wherein a P type semiconductor well region is provided at an upper level of an N type silicon substrate, said plurality of pixels are provided in an N type semiconductor region located at a layer on the upper side of said P type semiconductor well region, and P type semiconductor well regions for device separation are provided at boundary portions between adjacent pixels.
 8. A solid state image pickup device as set forth in claim 1, comprising a floating diffusion for taking out signal charge generated by said photo-electric conversion element, and a transfer transistor for transferring said signal charge generated by said photo-electric conversion element to said floating diffusion portion.
 9. A solid state image pickup device as set forth in claim 8, further comprising an amplification transistor for converting a potential variation in said floating diffusion portion into an electric signal.
 10. A solid state image pickup device as set forth in claim 9, further comprising a reset transistor for resetting the potential of said floating diffusion portion.
 11. A solid state image pickup device as set forth in claim 10, which further comprises a selection transistor for selecting an output of said amplification transistor.
 12. A solid state image pickup device having a plurality of pixels comprising: a photo-electric conversion element; a insulating film formed between adjacent pixels, a first well region formed under said insulating film between adjacent pixels; a second well region formed under said first well region; and wherein a width of said second region is narrower than that of said first region.
 13. A solid state image pick up device as set forth in claim 12, further comprising: a third well region formed below said second well region.
 14. A solid state image pick up device as set forth in claim 12, wherein said photo-electric conversion device is a photodiode.
 15. A solid state image pick up device as set forth in claim 12, further comprising: a fourth well region, which is opposite conductivity type of said second well region, formed on said substrate; and wherein an impurity density of said fourth well region is lower than that of second well region.
 16. A solid state image pickup device having a plurality of pixels comprising: a semiconductor material of a first conductivity type; a first well region of a second conductivity type formed above said semiconductor material; a second well region of said first conductivity type formed above said first well region; a photo-electric conversion device formed between said second well region; a MOS transistor formed within said second well region; an isolation layer formed between said pixels; wherein said isolation layer is comprised of a first and second layers, and said first layers has a bigger area than that of second area.
 17. A solid state image pick up device as set forth in claim 16; further comprising: an isolation region formed between adjacent pixels; and wherein said isolation region is contained within said first layer.
 18. A solid state image pick up device as set forth in claim 17; wherein said MOS transistor has a channel layer of said second conductivity type and a drain region; and wherein said drain region is formed as a floating diffusion.
 19. A solid state image pick up device as set forth in claim 18, wherein said floating is close to said first layer.
 20. A solid state image pick up device as set forth in claim 16: wherein said photo-electric conversion layer is comprised of a first semiconductor region of said second conductivity type and a second semiconductor region of said first conductivity type; and wherein said second semiconductor region is comprised of a plurality of layers. 